iommu/arm-smmu: Fix the values of ARM64_TCR_{I,O}RGN0_SHIFT

This change “iommu/arm-smmu: Fix the values of ARM64_TCR_{I,O}RGN0_SHIFT” (commit 5d58c62) in Linux kernel is authored by Zhen Lei <thunder.leizhen [at] huawei.com> on Fri Jun 26 09:32:59 2015 +0100.

Description of "iommu/arm-smmu: Fix the values of ARM64_TCR_{I,O}RGN0_SHIFT"

The change “iommu/arm-smmu: Fix the values of ARM64_TCR_{I,O}RGN0_SHIFT” introduces changes as follows.

iommu/arm-smmu: Fix the values of ARM64_TCR_{I,O}RGN0_SHIFT

The arm64 CPU architecture defines TCR[8:11] as holding the inner and
outer memory attributes for TTBR0.

This patch fixes the ARM SMMUv3 driver to pack these bits into the
context descriptor, rather than picking up the TTBR1 attributes as it
currently does.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

Linux kernel releases containing commit 5d58c62

The Linux kernel releases containing this commit are as follows.

Linux kernel code changes from "iommu/arm-smmu: Fix the values of ARM64_TCR_{I,O}RGN0_SHIFT"

There are 4 lines of Linux source code added/deleted in this change. Code changes to Linux kernel are as follows.

 drivers/iommu/arm-smmu-v3.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
 
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 6b1ae4e09616..98e987a3ed3a 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -269,10 +269,10 @@
 #define ARM64_TCR_TG0_SHIFT		14
 #define ARM64_TCR_TG0_MASK		0x3UL
 #define CTXDESC_CD_0_TCR_IRGN0_SHIFT	8
-#define ARM64_TCR_IRGN0_SHIFT		24
+#define ARM64_TCR_IRGN0_SHIFT		8
 #define ARM64_TCR_IRGN0_MASK		0x3UL
 #define CTXDESC_CD_0_TCR_ORGN0_SHIFT	10
-#define ARM64_TCR_ORGN0_SHIFT		26
+#define ARM64_TCR_ORGN0_SHIFT		10
 #define ARM64_TCR_ORGN0_MASK		0x3UL
 #define CTXDESC_CD_0_TCR_SH0_SHIFT	12
 #define ARM64_TCR_SH0_SHIFT		12

The commit for this change in Linux stable tree is 5d58c62 (patch).

Last modified: 2020/02/09