arm64: tegra: Fix AGIC register range [Linux 4.9.187]

This Linux kernel change "arm64: tegra: Fix AGIC register range" is included in the Linux 4.9.187 release. This change is authored by Jon Hunter <jonathanh [at] nvidia.com> on Thu Jun 20 09:17:00 2019 +0100. The commit for this change in Linux stable tree is 39dd595 (patch) which is from upstream commit ba24eee. The same Linux upstream change may have been applied to various maintained Linux releases and you can find all Linux releases containing changes from upstream ba24eee.

arm64: tegra: Fix AGIC register range

commit ba24eee6686f6ed3738602b54d959253316a9541 upstream.

The Tegra AGIC interrupt controller is an ARM GIC400 interrupt
controller. Per the ARM GIC device-tree binding, the first address
region is for the GIC distributor registers and the second address
region is for the GIC CPU interface registers. The address space for
the distributor registers is 4kB, but currently this is incorrectly
defined as 8kB for the Tegra AGIC and overlaps with the CPU interface
registers. Correct the address space for the distributor to be 4kB.

Cc: stable@vger.kernel.org
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Fixes: bcdbde433542 ("arm64: tegra: Add AGIC node for Tegra210")
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

There are 2 lines of Linux source code added/deleted in this change. Code changes to Linux kernel are as follows.

 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 46045fe..87ef72b 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1020,7 +1020,7 @@
            compatible = "nvidia,tegra210-agic";
            #interrupt-cells = <3>;
            interrupt-controller;
-           reg = <0x702f9000 0x2000>,
+           reg = <0x702f9000 0x1000>,
                  <0x702fa000 0x2000>;
            interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
            clocks = <&tegra_car TEGRA210_CLK_APE>;

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