arm64: cpufeature: Fix CTR_EL0 field definitions [Linux 4.9.189]

This Linux kernel change "arm64: cpufeature: Fix CTR_EL0 field definitions" is included in the Linux 4.9.189 release. This change is authored by Will Deacon <will.deacon [at] arm.com> on Mon Aug 5 18:13:54 2019 +0100. The commit for this change in Linux stable tree is e364e9a (patch) which is from upstream commit be68a8a. The same Linux upstream change may have been applied to various maintained Linux releases and you can find all Linux releases containing changes from upstream be68a8a.

arm64: cpufeature: Fix CTR_EL0 field definitions

commit be68a8aaf925aaf35574260bf820bb09d2f9e07f upstream.

Our field definitions for CTR_EL0 suffer from a number of problems:

  - The IDC and DIC fields are missing, which causes us to enable CTR
    trapping on CPUs with either of these returning non-zero values.

  - The ERG is FTR_LOWER_SAFE, whereas it should be treated like CWG as
    FTR_HIGHER_SAFE so that applications can use it to avoid false sharing.

  - [nit] A RES1 field is described as "RAO"

This patch updates the CTR_EL0 field definitions to fix these issues.

Cc: <[email protected]> # 4.9.y only
Cc: Shanker Donthineni <s[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Sasha Levin <[email protected]>

There are 8 lines of Linux source code added/deleted in this change. Code changes to Linux kernel are as follows.

 arch/arm64/kernel/cpufeature.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index a3ab7df..e2ac72b 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -148,10 +148,12 @@
 };

 static const struct arm64_ftr_bits ftr_ctr[] = {
-   ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1),    /* RAO */
-   ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
+   ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1),    /* RES1 */
+   ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 30, 1, 0),
+   ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1),   /* DIC */
+   ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1),   /* IDC */
    ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),  /* CWG */
-   ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),   /* ERG */
+   ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 20, 4, 0),  /* ERG */
    ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
    /*
     * Linux can handle differing I-cache policies. Userspace JITs will

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