x86: cpufeatures: Renumber feature word 7 [Linux 3.16.72]

This Linux kernel change "x86: cpufeatures: Renumber feature word 7" is included in the Linux 3.16.72 release. This change is authored by Ben Hutchings <ben [at] decadent.org.uk> on Thu Aug 8 20:11:40 2019 +0100. The commit for this change in Linux stable tree is e3b7a57 (patch).

x86: cpufeatures: Renumber feature word 7

Use the same bit numbers for all features that are also present in
4.4.y and 4.9.y, to make further backports slightly easier.

Signed-off-by: Ben Hutchings <[email protected]>

There are 39 lines of Linux source code added/deleted in this change. Code changes to Linux kernel are as follows.

 arch/x86/include/asm/cpufeatures.h | 39 ++++++++++++++++++++------------------
 1 file changed, 21 insertions(+), 18 deletions(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 99137cb..5805181 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -177,29 +177,32 @@
 #define X86_FEATURE_ARAT   ( 7*32+ 1) /* Always Running APIC Timer */
 #define X86_FEATURE_CPB        ( 7*32+ 2) /* AMD Core Performance Boost */
 #define X86_FEATURE_EPB        ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
-#define X86_FEATURE_XSAVEOPT   ( 7*32+ 4) /* Optimized Xsave */
+#define X86_FEATURE_INVPCID_SINGLE ( 7*32+4) /* Effectively INVPCID && CR4.PCIDE=1 */
 #define X86_FEATURE_PLN        ( 7*32+ 5) /* Intel Power Limit Notification */
 #define X86_FEATURE_PTS        ( 7*32+ 6) /* Intel Package Thermal Status */
 #define X86_FEATURE_DTHERM ( 7*32+ 7) /* Digital Thermal Sensor */
 #define X86_FEATURE_HW_PSTATE  ( 7*32+ 8) /* AMD HW-PState */
 #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
-#define X86_FEATURE_INVPCID_SINGLE ( 7*32+10) /* Effectively INVPCID && CR4.PCIDE=1 */
-#define X86_FEATURE_RSB_CTXSW  ( 7*32+11) /* "" Fill RSB on context switches */
-#define X86_FEATURE_USE_IBPB   ( 7*32+12) /* "" Indirect Branch Prediction Barrier enabled */
-#define X86_FEATURE_USE_IBRS_FW ( 7*32+13) /* "" Use IBRS during runtime firmware calls */
-#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+14) /* "" Disable Speculative Store Bypass. */
-#define X86_FEATURE_LS_CFG_SSBD    ( 7*32+15) /* "" AMD SSBD implementation */
-#define X86_FEATURE_IBRS   ( 7*32+16) /* Indirect Branch Restricted Speculation */
-#define X86_FEATURE_IBPB   ( 7*32+17) /* Indirect Branch Prediction Barrier */
-#define X86_FEATURE_STIBP  ( 7*32+18) /* Single Thread Indirect Branch Predictors */
-#define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+19) /* "" MSR SPEC_CTRL is implemented */
-#define X86_FEATURE_SSBD   ( 7*32+20) /* Speculative Store Bypass Disable */
-#define X86_FEATURE_ZEN        ( 7*32+21) /* "" CPU is AMD family 0x17 (Zen) */
-#define X86_FEATURE_L1TF_PTEINV    ( 7*32+22) /* "" L1TF workaround PTE inversion */
-#define X86_FEATURE_IBRS_ENHANCED ( 7*32+23) /* Enhanced IBRS */
-#define X86_FEATURE_RETPOLINE  ( 7*32+29) /* "" Generic Retpoline mitigation for Spectre variant 2 */
-#define X86_FEATURE_RETPOLINE_AMD ( 7*32+30) /* "" AMD Retpoline mitigation for Spectre variant 2 */
-/* Because the ALTERNATIVE scheme is for members of the X86_FEATURE club... */
+
+#define X86_FEATURE_RETPOLINE  ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
+#define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */
+
+#define X86_FEATURE_XSAVEOPT   ( 7*32+15) /* Optimized Xsave */
+#define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */
+#define X86_FEATURE_SSBD   ( 7*32+17) /* Speculative Store Bypass Disable */
+
+#define X86_FEATURE_RSB_CTXSW  ( 7*32+19) /* "" Fill RSB on context switches */
+
+#define X86_FEATURE_USE_IBPB   ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
+#define X86_FEATURE_USE_IBRS_FW ( 7*32+22) /* "" Use IBRS during runtime firmware calls */
+#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */
+#define X86_FEATURE_LS_CFG_SSBD    ( 7*32+24) /* "" AMD SSBD implementation */
+#define X86_FEATURE_IBRS   ( 7*32+25) /* Indirect Branch Restricted Speculation */
+#define X86_FEATURE_IBPB   ( 7*32+26) /* Indirect Branch Prediction Barrier */
+#define X86_FEATURE_STIBP  ( 7*32+27) /* Single Thread Indirect Branch Predictors */
+#define X86_FEATURE_ZEN        ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */
+#define X86_FEATURE_L1TF_PTEINV    ( 7*32+29) /* "" L1TF workaround PTE inversion */
+#define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
 #define X86_FEATURE_KAISER ( 7*32+31) /* CONFIG_PAGE_TABLE_ISOLATION w/o nokaiser */

 /* Virtualization flags: Linux defined, word 8 */

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