Revert "drm/amd/display: Add Underflow Asserts to dc" [Linux 5.3]

This Linux kernel change "Revert “drm/amd/display: Add Underflow Asserts to dc”" is included in the Linux 5.3 release. This change is authored by Alex Deucher <alexander.deucher [at] amd.com> on Mon Jun 17 13:06:19 2019 -0500. The commit for this change in Linux stable tree is 0198b6e (patch).

Revert "drm/amd/display: Add Underflow Asserts to dc"

This reverts commit 9ed43ef84d9d1e668acdf43c95510fb7b11f8d71.

Revert this to apply the version that includes DCN2 support.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

There are 40 lines of Linux source code added/deleted in this change. Code changes to Linux kernel are as follows.

 drivers/gpu/drm/amd/display/dc/dc.h                |  1 -
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 32 +---------------------
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h  |  2 --
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  4 +--
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |  1 -
 5 files changed, 2 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 9aa01bf8..ffd1fe5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -329,7 +329,6 @@ struct dc_debug_options {
    int sr_exit_time_ns;
    int sr_enter_plus_exit_time_ns;
    int urgent_latency_ns;
-   uint32_t underflow_assert_delay_us;
    int percent_of_ideal_drambw;
    int dram_clock_change_latency_ns;
    bool optimized_watermark;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 1ac9a4f..316e0da 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -361,23 +361,6 @@ void dcn10_log_hw_state(struct dc *dc,
    DTN_INFO_END();
 }

-bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
-{
-   struct hubp *hubp = pipe_ctx->plane_res.hubp;
-   struct timing_generator *tg = pipe_ctx->stream_res.tg;
-
-   if (tg->funcs->is_optc_underflow_occurred(tg)) {
-       tg->funcs->clear_optc_underflow(tg);
-       return true;
-   }
-
-   if (hubp->funcs->hubp_get_underflow_status(hubp)) {
-       hubp->funcs->hubp_clear_underflow(hubp);
-       return true;
-   }
-   return false;
-}
-
 static void enable_power_gating_plane(
    struct dce_hwseq *hws,
    bool enable)
@@ -2350,7 +2333,6 @@ static void dcn10_apply_ctx_for_surface(
 {
    int i;
    struct timing_generator *tg;
-   uint32_t underflow_check_delay_us;
    bool removed_pipe[4] = { false };
    bool interdependent_update = false;
    struct pipe_ctx *top_pipe_to_program =
@@ -2365,22 +2347,11 @@ static void dcn10_apply_ctx_for_surface(
    interdependent_update = top_pipe_to_program->plane_state &&
        top_pipe_to_program->plane_state->update_flags.bits.full_update;

-   underflow_check_delay_us = dc->debug.underflow_assert_delay_us;
-
-   if (underflow_check_delay_us != 0xFFFFFFFF && dc->hwss.did_underflow_occur)
-       ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
-
    if (interdependent_update)
        lock_all_pipes(dc, context, true);
    else
        dcn10_pipe_control_lock(dc, top_pipe_to_program, true);

-   if (underflow_check_delay_us != 0xFFFFFFFF)
-       udelay(underflow_check_delay_us);
-
-   if (underflow_check_delay_us != 0xFFFFFFFF && dc->hwss.did_underflow_occur)
-       ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
-
    if (num_planes == 0) {
        /* OTG blank before remove all front end */
        dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
@@ -3052,8 +3023,7 @@ static void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
    .disable_stream_gating = NULL,
    .enable_stream_gating = NULL,
    .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
-   .setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
-   .did_underflow_occur = dcn10_did_underflow_occur
+   .setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt
 };

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index d3616b1..ef94d6b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -71,8 +71,6 @@ void dcn10_get_hdr_visual_confirm_color(
        struct pipe_ctx *pipe_ctx,
        struct tg_color *color);

-bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);
-
 void update_dchubp_dpp(
    struct dc *dc,
    struct pipe_ctx *pipe_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 29fd3cb..f6004bc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -560,7 +560,6 @@ enum dcn10_clk_src_array_id {
        .az_endpoint_mute_only = true,
        .recovery_enabled = false, /*enable this by default after testing.*/
        .max_downscale_src_width = 3840,
-       .underflow_assert_delay_us = 0xFFFFFFFF,
 };

 static const struct dc_debug_options debug_defaults_diags = {
@@ -570,8 +569,7 @@ enum dcn10_clk_src_array_id {
        .clock_trace = true,
        .disable_stutter = true,
        .disable_pplib_clock_request = true,
-       .disable_pplib_wm_range = true,
-       .underflow_assert_delay_us = 0xFFFFFFFF,
+       .disable_pplib_wm_range = true
 };

 static void dcn10_dpp_destroy(struct dpp **dpp)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index dab0168..eb1c12e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -240,7 +240,6 @@ struct hw_sequencer_funcs {

    void (*setup_periodic_interrupt)(struct pipe_ctx *pipe_ctx, enum vline_select vline);
    void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx);
-   bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);

 };

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