Documentation: x86: Remove cdpl2 unspported statement and fix capitalisation [Linux 5.3]

This Linux kernel change "Documentation: x86: Remove cdpl2 unspported statement and fix capitalisation" is included in the Linux 5.3 release. This change is authored by James Morse <james.morse [at] arm.com> on Fri Jun 7 16:14:07 2019 +0100. The commit for this change in Linux stable tree is 7c7a499 (patch).

Documentation: x86: Remove cdpl2 unspported statement and fix capitalisation

"L2 cache does not support code and data prioritization". This isn't
true, elsewhere the document says it can be enabled with the cdpl2
mount option.

While we're here, these sample strings have lower-case code/data,
which isn't how the kernel exports them.

Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>

There are 14 lines of Linux source code added/deleted in this change. Code changes to Linux kernel are as follows.

 Documentation/x86/resctrl_ui.rst | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/Documentation/x86/resctrl_ui.rst b/Documentation/x86/resctrl_ui.rst
index 066f94e..638cd98 100644
--- a/Documentation/x86/resctrl_ui.rst
+++ b/Documentation/x86/resctrl_ui.rst
@@ -418,16 +418,22 @@ L3 schemata file details (CDP enabled via mount option to resctrl)
 When CDP is enabled L3 control is split into two separate resources
 so you can specify independent masks for code and data like this::

-   L3data:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
-   L3code:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
+   L3DATA:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
+   L3CODE:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...

 L2 schemata file details
 ------------------------
-L2 cache does not support code and data prioritization, so the
-schemata format is always::
+CDP is supported at L2 using the 'cdpl2' mount option. The schemata
+format is either::

    L2:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...

+or
+
+   L2DATA:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
+   L2CODE:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
+
+
 Memory bandwidth Allocation (default mode)
 ------------------------------------------

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